1. Field of the Invention
The present invention relates to a chip package structure and process of fabricating the same. More particularly, the present invention relates to a chip package structure and process of fabricating the same that deploys a flip chip bonding technique.
2. Description of the Related Art
In this information world, the market for electronic devices is expanding at a rapid pace. To sustain this expansion, the chip packaging techniques need to reflects the trend for more digital circuits, network capabilities, local connectivity and customization. These demands in turn reflect the need to increase the processing speed of the electronic devices, miniaturize and increase the level of integration of these devices, incorporate more functions into each package and lower the production cost of each package. As a result, more miniaturized and high-density chip packages are produced. In the flip-chip technique, bumps instead of wires are used to connect a chip and a carrier together so that the average wiring length in a flip chip package is reduced. Since the transmission speed of signals between the chip and the carrier is significantly improved, flip chip packages have gradually become mainstream high-density packages.
FIG. 1 is a schematic cross-sectional view of a chip package structure fabricated using a conventional flip-chip bonding technique. As shown in FIG. 1, the chip package structure 40 mainly comprises a chip 50, a carrier 80 and a plurality of bumps 60. The chip 50 in the chip package structure 40 has an active surface 52 and the active surface 52 has a plurality of bonding pads 54 disposed thereon. The carrier 80 has a plurality of contacts 84 disposed thereon. The bumps 60 are disposed on the bonding pads 54 on the active surface 52 of the chip 50. The chip 50 is electrically connected to the carrier 80 through the bonding pads 54, the bumps 60 and the contacts 84.
To prevent possible damage to the chip 50 due to moisture incursion or possible damage to the bumps 60 which connect the chip 50 and the carrier 80 together due to mechanical stress, an underfill layer 70 is also formed between the chip 50 and the carrier 80. However, the chip 50, the bumps 60, the underfill layer 70 and the carrier 80 all have different coefficient of thermal expansion (CTE). Through cyclic temperature changes in processing operations, the chip package structure 40 may ultimately fail as a result of cumulative thermal stress.
In general, the upper layer of most chips is a metallic interconnect structure comprising a plurality of conductive layers and dielectric layers alternately laid over each other. When the Young's modulus E of the underfill layer is high, thermal stress will force a delamination between the conductive layer and the dielectric layer from each other leading to a damage to the metallic interconnect structure. With the application of copper processing technique in semiconductor chip production, the conventional materials constituting the conductive layer and dielectric layer have already changed from aluminum and silicon dioxide to copper and organic compound. Since the adhesive strength between copper and the low dielectric constant (low k) dielectric layer is worse than the adhesive strength between aluminum and silicon dioxide, the delamination between a copper conductive layer and a low dielectric constant dielectric layer under thermal stress will occur more frequently.
In brief, minimizing possible damage to the metallic interconnect structure inside a chip resulting from differences in coefficient of thermal expansion between various components inside a package, including the chip, the bumps, the underfill layer and the carrier, is an important research topic.